View LTC2865_7893054.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 for more information www.linear.com/ltc2862 typical a pplica t ion descrip t ion 60 v fault protected 3 v to 5.5v rs485/rs422 transceivers rs485 link with large ground loop voltage fea t ures a pplica t ions n protected from overvoltage line faults to 60v n 3v to 5.5v supply voltage n 20mbps or low emi 250kbps data rate n 15kv esd interface pins, 8kv all other pins n extended common mode range: 25v n guaranteed failsafe receiver operation n high input impedance supports 256 nodes n 1.65v to 5.5v logic supply pin (v l ) for flexible digital interface (LTC2865) n mp-grade option available (C55c to 125c) n fully balanced differential receiver thresholds for low duty cycle distortion n current limited drivers and thermal shutdown n pin compatible with lt1785 and lt1791 n available in dfn and leaded packages n supervisory control and data acquisition (scada) n industrial control and instrumentation networks n automotive and transportation electronics n building automation, security systems and hvac n medical equipment n lighting and sound system control LTC2865 receiving 10mbps 200mv differential signal with 1mhz 25v common mode sweep part number duplex enables ma x data rate ( bps ) v l pin ltc 2862 -1 half yes 20 m no ltc 2862 -2 half yes 250 k no ltc 2863 -1 full no 20 m no ltc 2863 -2 full no 250 k no ltc 2864 -1 full yes 20 m no ltc 2864 -2 full yes 250 k no ltc 2865 full yes 20 m /250 k yes the lt c ? 2862/ltc2863 / ltc2864 / LTC2865 are low power , 20mbps or 250kbps rs485/rs422 transceivers operating on 3 v to 5.5 v supplies that feature 60 v overvoltage fault protection on the data transmission lines during all modes of operation, including power-down. low emi slew rate limited data transmission is available in a logic-selectable 250kbps mode in the LTC2865 and in 250 kbps versions of the ltc2862-ltc2864. enhanced esd protection allows these parts to withstand 15 kv hbm on the transceiver interface pins without latchup or damage. extended 25 v input common mode range and full fail - safe operation improve data communication reliability in electrically noisy environments and in the presence of large ground loop voltages. l, lt , lt c , lt m , linear technology the linear logo and module are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. p ro d uc t s elec t ion gui d e gnd1 gnd2 2862345 ta01a r t r t ro1 re1 de1 di1 vcc1 ltc2862 ltc2862 vcc2 ro2 re2 de2 di2 d d r r v ground loop 25v peak a,b 50v/div a-b 0.5v/div 100ns/div 2862345 ta01b ro 5v/div ro a,b a-b 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
2 for more information www.linear.com/ltc2862 a bsolu t e maxi m u m r a t in g s supply voltages v cc ............................................................. C0.3 to 6v v l .............................................................. C0. 3 to 6v logic input voltages ( re , de , di , slo ) .......... C 0.3 to 6v interface i/o: a, b, y, z .............................. C 60 v to +60 v receiver output ( ro ) ( lt c 2862 - ltc 2864 ) ................... C 0.3 v to (v cc +0.3 v) receiver output ( ro ) ( lt c 2865 ) .................................. C0. 3 v to (v l + 0.3 v) operating ambient temperature range ( note 4) ltc 28 6 xc ................................................ 0 c to 70 c ltc 28 6 xi ............................................. C 40 c to 85 c ltc 28 6 xh .......................................... C 40 c to 125 c ltc 28 6 x mp ....................................... C 55 c to 125 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 30 0 c p in c on f i g ura t ion ltc 2862 -1, ltc 2862 -2 ltc 2862 -1, ltc 2862 -2 1 2 3 4 8 7 6 5 top view v cc b a gnd ro re de di s8 package 8-lead (150mil) plastic so t jmax = 150c, ja = 150c/w, jc = 39c/w top view dd package 8-lead (3mm 3mm) plastic dfn exposed pad (pin 9) connect to pcb gnd t jmax = 150c, ja = 43c/w, jc = 3c/w 5 6 7 8 9 4 3 2 1ro re de di v cc b a gnd ltc 2863 -1, ltc 2863 -2 ltc 2863 -1, ltc 2863 -2 1 2 3 4 8 7 6 5 top view a b z y v cc ro di gnd s8 package 8-lead (150mil) plastic so t jmax = 150c, ja = 150c/w, jc = 39c/w top view dd package 8-lead (3mm 3mm) plastic dfn exposed pad (pin 9) connect to pcb gnd t jmax = 150c, ja = 43c/w, jc = 3c/w 5 6 7 8 9 4 3 2 1v cc ro di gnd a b z y ltc 2864 -1, ltc 2864 -2 ltc 2864 -1, ltc 2864 -2 top view s package 14-lead (150mil) plastic so t jmax = 150c, ja = 88c/w, jc = 37c/w 1 2 3 4 5 6 7 14 13 12 11 10 9 8 nc ro re de di gnd gnd v cc nc a b z y nc top view dd package 10-lead (3mm 3mm) plastic dfn exposed pad (pin 11) connect to pcb gnd t jmax = 150c, ja = 43c/w, jc = 3c/w 10 9 6 7 8 4 5 3 2 1 v cc a b z y ro re de di gnd 11 (note 1) 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
3 for more information www.linear.com/ltc2862 o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc2862cs8-1#pbf ltc2862cs8-1#trpbf 28621 8-lead (150mil) plastic so 0c to 70c ltc2862is8-1#pbf ltc2862is8-1#trpbf 28621 8-lead (150mil) plastic so C40c to 85c ltc2862hs8-1#pbf ltc2862hs8-1#trpbf 28621 8-lead (150mil) plastic so C40c to 125c ltc2862cs8-2#pbf ltc2862cs8-2#trpbf 28622 8-lead (150mil) plastic so 0c to 70c ltc2862is8-2#pbf ltc2862is8-2#trpbf 28622 8-lead (150mil) plastic so C40c to 85c ltc2862hs8-2#pbf ltc2862hs8-2#trpbf 28622 8-lead (150mil) plastic so C40c to 125c ltc2862cdd-1#pbf ltc2862cdd-1#trpbf lfxk 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc2862idd-1#pbf ltc2862idd-1#trpbf lfxk 8-lead (3mm 3mm) plastic dfn C40c to 85c ltc2862hdd-1#pbf ltc2862hdd-1#trpbf lfxk 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc2862cdd-2#pbf ltc2862cdd-2#trpbf lfxm 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc2862idd-2#pbf ltc2862idd-2#trpbf lfxm 8-lead (3mm 3mm) plastic dfn C40c to 85c ltc2862hdd-2#pbf ltc2862hdd-2#trpbf lfxm 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc2863cs8-1#pbf ltc2863cs8-1#trpbf 28631 8-lead (150mil) plastic so 0c to 70c ltc2863is8-1#pbf ltc2863is8-1#trpbf 28631 8-lead (150mil) plastic so C40c to 85c ltc2863hs8-1#pbf ltc 2863hs8-1#trpbf 28631 8- lead (150mil) plastic so C40c to 125c ltc2863cs8-2#pbf ltc2863cs8-2#trpbf 28632 8-lead (150mil) plastic so 0c to 70c ltc2863is8-2#pbf ltc2863is8-2#trpbf 28632 8-lead (150mil) plastic so C40c to 85c ltc2863hs8-2#pbf ltc2863hs8-2#trpbf 28632 8-lead (150mil) plastic so C40c to 125c ltc2863cdd-1#pbf ltc2863cdd-1#trpbf lfxn 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc2863idd-1#pbf ltc2863idd-1#trpbf lfxn 8-lead (3mm 3mm) plastic dfn C40c to 85c ltc2863hdd-1#pbf ltc2863hdd-1#trpbf lfxn 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc2863cdd-2#pbf ltc2863cdd-2#trpbf lfxp 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc2863idd-2#pbf ltc2863idd-2#trpbf lfxp 8-lead (3mm 3mm) plastic dfn C40c to 85c ltc2863hdd-2#pbf ltc2863hdd-2#trpbf lfxp 8-lead (3mm 3mm) plastic dfn C40c to 125c pin con f i g ura t ion ltc 2865 ltc 2865 1 2 3 4 5 6 ro re de di v l gnd 12 11 10 9 8 7 v cc a b z y slo top view mse package 12-lead plastic msop exposed pad (pin 13) connect to pcb gnd t jmax = 150c, ja = 40c/w, jc = 10c/w 13 12 11 10 9 8 7 13 1 2 3 4 5 6 v cc a b z y slo ro re de di v l gnd top view de package 12-lead (4mm 3mm) plastic dfn exposed pad (pin 13) connect to pcb gnd t jmax = 150c, ja = 43c/w, jc = 4.3c/w 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
4 for more information www.linear.com/ltc2862 lead free finish tape and reel part marking* package description temperature range ltc2864cs-1#pbf ltc2864cs-1#trpbf ltc2864s-1 14-lead (150mil) plastic so 0c to 70c ltc2864is-1#pbf ltc2864is-1#trpbf ltc2864s-1 14-lead (150mil) plastic so C40c to 85c ltc2864hs-1#pbf ltc2864hs-1#trpbf ltc2864s-1 14-lead (150mil) plastic so C40c to 125c ltc2864cs-2#pbf ltc2864cs-2#trpbf ltc2864s-2 14-lead (150mil) plastic so 0c to 70c ltc2864is-2#pbf ltc2864is-2#trpbf ltc2864s-2 14-lead (150mil) plastic so C40c to 85c ltc2864hs-2#pbf ltc2864hs-2#trpbf ltc2864s-2 14-lead (150mil) plastic so C40c to 125c ltc2864cdd-1#pbf ltc2864cdd-1#trpbf lfxq 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2864idd-1#pbf ltc2864idd-1#trpbf lfxq 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2864hdd-1#pbf ltc2864hdd-1#trpbf lfxq 10-lead (3mm 3mm) plastic dfn C40c to 125c ltc2864cdd-2#pbf ltc2864cdd-2#trpbf lfxr 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2864idd-2#pbf ltc2864idd-2#trpbf lfxr 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2864hdd-2#pbf ltc2864hdd-2#trpbf lfxr 10-lead (3mm 3mm) plastic dfn C40c to 125c LTC2865cmse#pbf LTC2865cmse#trpbf 2865 12-lead plastic msop 0c to 70c LTC2865imse#pbf LTC2865imse#trpbf 2865 12-lead plastic msop C40 c to 85c LTC2865hmse#pbf LTC2865hmse#trpbf 2865 12-lead plastic msop C40c to 125c LTC2865cde#pbf LTC2865cde#trpbf 2865 12-lead (4mm 3mm) plastic dfn 0c to 70c LTC2865ide#pbf LTC2865ide#trpbf 2865 12-lead (4mm 3mm) plastic dfn C40c to 85c LTC2865hde#pbf LTC2865hde#trpbf 2865 12-lead (4mm 3mm) plastic dfn C40c to 125c ltc2862mps8-1#pbf ltc2862mps8-1#trpbf 28621 8-lead (150mm) plastic so C55c to 125c ltc2862mps8-2#pbf ltc2862mps8-2#trpbf 28622 8-lead (150mm) plastic so C55c to 125c ltc2863mps8-1#pbf ltc2863mps8-1#trpbf 28631 8-lead (150mm) plastic so C55c to 125c ltc2863mps8-2#pbf ltc2863mps8-2#trpbf 28632 8-lead (150mm) plastic so C55c to 125c ltc2864mps-1#pbf ltc2864mps-1#trpbf ltc2864s-1 14-lead (150mm) plastic so C55c to 125c ltc2864mps-2#pbf ltc2864mps-2#trpbf ltc2864s-2 14-lead (150mm) plastic so C55c to 125c consult lt c marketing for parts specified with wider operating temperature ranges . *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ or d er in f or m a t ion e lec t rical c harac t eris t ics symbol parameter conditions min typ max units supplies v cc primary power supply l 3 5.5 v v l logic interface power supply LTC2865 only l 1.65 v cc v i ccs supply current in shutdown mode (c-, i-grade) (n/a ltc2863) de = 0v, re = v cc = v l l 0 5 a supply current in shutdown mode (h-, mp-grade) (n/a ltc2863) de = 0v, re = v cc = v l l 0 40 a i cctr supply current with both driver and receiver enabled (ltc2862-1, ltc2863-1, ltc2864-1, LTC2865 with slo high) no load, de = v cc = v l , re = 0v l 900 1300 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = v l = 3.3v unless otherwise noted. (note 2) 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
5 for more information www.linear.com/ltc2862 symbol parameter conditions min typ max units i cctrs supply current with both driver and receiver enabled (ltc2862-2, ltc2863-2, ltc2864-2, LTC2865 with slo low) no load, de = v cc = v l , re = 0v l 3.3 8 ma driver |v od | differential driver output voltage r = (figure 1) l 1.5 v cc v r = 27 (figure 1) l 1.5 5 v r = 50 (figure 1) l 2 v cc v |v od | change in magnitude of driver differential output voltage r = 27 or 50 (figure 1) l 0.2 v v oc driver common-mode output voltage r = 27 or 50 (figure 1) l 3 v |v oc | change in magnitude of driver common-mode output voltage r = 27 or 50 (figure 1) l 0.2 v i osd maximum driver short-circuit current C60v (y or z) 60v (figure 2) l 150 250 ma i ozd driver three-state (high impedance) output current on y and z de = 0v , v cc = 0 v or 3.3v , v o = C25 v, 25v l 30 a receiver i in receiver input current (a,b) (c-, i-grade ltc2863, ltc2864, LTC2865) v cc = 0v or 3.3v, v in = 12v (figure 3) l 125 a a v cc = 0v or 3.3v, v in = C7v (figure 3) l C100 receiver input current (a,b) (h-, mp-grade ltc2863, ltc2864, LTC2865; c-, i-, h-, mp-grade ltc2862) v cc = 0v or 3.3v, v in = 12v (figure 3) l 143 a a v cc = 0v or 3.3v, v in = C7v (figure 3) l C100 r in receiver input resistance 0 v cc 5.5v, v in = C25v or 25v (figure 3) 112 k v cm receiver common mode input voltage (a + b)/2 l C25 25 v v th differential input signal threshold voltage (a C b) C25 v v cm 25v l 200 mv v th differential input signal hysteresis v cm = 0v 150 mv differential input failsafe threshold voltage C25v v cm 25v l C200 C50 0 mv differential input failsafe hysteresis v cm = 0v 25 mv v oh receiver output high voltage i(ro) = C3ma (sourcing) v l 2.25v, i(ro) = C3ma (LTC2865) v l < 2.25v, i(ro) = C2ma (LTC2865) l l l v cc C0.4v v l C0.4v v l C0.4v v v ol receiver output low voltage i(ro) = 3ma (sinking) l 0.4 v i ozr receiver three-state (high impedance) output current on ro re = high, ro = 0v or v cc ro = 0v or v l (LTC2865) l 5 a i osr receiver short-circuit current re = low, ro = 0v or v cc ro = 0v or v l (LTC2865) l 20 ma logic ( ltc2862, ltc2863, ltc2864) v th input threshold voltage (de, di, re ) 3.0 v cc 5.5v l 0.33 ? v cc 0.67 ? v cc v i inl logic input current (de, di, re) 0 v in v cc l 0 5 a logic ( LTC2865) v th input threshold voltage (de, di, re, slo ) 1.65v v l 5.5v l 0.33 ? v l 0.67 ? v l v i inl logic input current (de, di, re, slo ) 0 v in v l l 0 5 a e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = v l = 3.3v unless otherwise noted. (note 2) 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
6 for more information www.linear.com/ltc2862 symbol parameter conditions min typ max units driver C high speed (ltc2862-1, ltc2863-1, ltc2864-1, LTC2865 with slo high) f max maximum data rate (note 3) l 20 mbps t plhd , t phld driver input to output r diff = 54, c l = 100pf (figure 4) l 25 50 ns t pd driver input to output difference |t plhd C t phld | r diff = 54, c l = 100pf (figure 4) l 2 9 ns t skewd driver output y to output z r diff = 54, c l = 100pf (figure 4) l 10 ns t rd , t fd driver rise or fall time r diff = 54, c l = 100pf (figure 4) l 4 15 ns t zld , t zhd , t lzd , t hzd driver enable or disable time r l = 500, c l = 50pf, re = 0v (figure 5) l 180 ns t zhsd , t zlsd driver enable from shutdown r l =500, c l = 50pf, re = high (figure 5) l 9 s t shdnd time to shutdown r l = 500, c l = 50pf, re = high (figure 5) l 180 ns driver C slew rate limited ( ltc2862-2, ltc2863-2, ltc2864-2, LTC2865 with slo low) f max maximum data rate (note 3) l 250 kbps t plhd , t phld driver input to output r diff = 54, c l = 100pf (figure 4) l 850 1500 ns t pd driver input to output difference |t plhd C t phld | r diff = 54, c l = 100pf (figure 4) l 50 500 ns t skewd driver output y to output z r diff = 54, c l = 100pf (figure 4) l 500 ns t rd , t fd driver rise or fall time r diff = 54, c l =100pf (figure 4) l 500 800 1200 ns t zld , t zhd driver enable time r l = 500, c l = 50pf, re = 0v (figure 5) l 1200 ns t lzd , t hzd driver disable time r l = 500, c l = 50pf, re = 0v (figure 5) l 180 ns t zhsd , t zlsd driver enable from shutdown r l = 500, c l = 50pf, re = high (figure 5) l 10 s t shdnd time to shutdown r l =500, c l = 50pf, re = high (figure 5) l 180 ns receiver t plhr , t phlr receiver input to output c l = 15 pf, v cm = 1.5v, |v ab | = 1.5v, t r and t f < 4ns (figure 6) l 50 65 ns t skewr differential receiver skew |t plhr C t phlr | c l = 15pf (figure 6) 2 9 ns t rr , t fr receiver output rise or fall time c l = 15pf (figure 6) l 3 12.5 ns t zlr , t zhr , t lzr , t hzr receiver enable/disable time r l = 1k , c l = 15 pf, de = high ( figure 7) l 40 ns t zhsr , t zlsr receiver enable from shutdown r l = 1k , c l = 15 pf, de = 0v , (figure 7) l 9 s t shdnr time to shutdown r l = 1k , c l = 15 pf, de = 0v , (figure 7) l 100 ns s wi t chin g c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = v l = 3.3v unless otherwise noted. (note 2) note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to device ground unless otherwise specified. note 3. maximum data rate is guaranteed by other measured parameters and is not tested directly. note 4. this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150oc when overtemperature protection is active. continuous operation above the specified maximum operating temperature may result in device degradation or failure. 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
7 for more information www.linear.com/ltc2862 typical p er f or m ance c harac t eris t ics driver output short-circuit current vs voltage driver output low/high voltage vs output current driver differential output voltage vs temperature supply current vs data rate driver skew vs temperature driver propagation delay vs temperature t a = 25c, v cc = v l = 3.3v, unless otherwise noted. supply current vs temperature supply current vs v cc output current (ma) 0 0.0 driver output voltage (v) 2.0 1.5 1.0 0.5 2.5 3.0 3.5 10 20 30 40 2862345 g07 50 v oh v ol temperature (c) ?50 1.5 v od (v) 1.9 1.7 2.1 2.3 2.5 0 50 100 2862345 g08 150 r diff = 100 r diff = 54 temperature (c) driver skew (slew limited) (ns) ?50 ?1.5 driver skew (non slew limited) (ns) 0.0 ?0.5 ?1.0 0.5 1.0 1.5 0 50 100 2862345 g04 150 0 60 40 20 100 80 120 slew limited non slew limited r diff = 54 c l = 100pf temperature (c) driver delay (slew limited) (ns) ?50 20 driver delay (non slew limited) (ns) 25 30 35 0 50 100 2862345 g05 150 700 800 900 1000 slew limited non slew limited r diff = 54 c l = 100pf v cc (v) 3.0 0 supply current (ma) 2.0 1.5 1.0 0.5 2.5 3.0 3.5 4.5 3.5 4.0 4.5 5.0 2862345 g01 5.5 4.0 i cctrs i cctr supply current (ma) data rate (slew limited) (kbps) 30 35 0 data rate (non slew limited) (mbps) 8 4 12 16 20 40 45 50 55 2862345 g03 60 0 100 50 200 150 250 slew limited non slew limited r diff = 54 c l = 100pf output voltage (v) ?60 ?200 output current (ma) 0 ?50 ?100 ?150 150 100 50 200 ?40 0?20 20 40 2862345 g06 60 output low output high temperature (c) ?50 0.1 supply current (a) 10 1 100 10000 0 50 100 2862345 g02 150 1000 i cctr i ccs i cctrs v l supply current vs data rate data rate (mbps) 0 0 v l supply current (a) 200 100 300 400 500 600 5 10 15 2862345 g09 20 c l (ro) = 15pf v cc = 5v v l = 5v v l = 2.5v v l = 3.3v v l = 1.8v 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
8 for more information www.linear.com/ltc2862 p in func t ions pin name pin number description ltc2862 ltc2863 ltc 2864 (dfn) ltc2864 (so) LTC2865 ro 1 2 1 2 1 receiver output. if the receiver output is enabled ( re low) and aCb > 200mv, then ro will be high. if aCb < C200mv, then ro will be low. if the receiver inputs are open, shorted, or terminated without a signal, ro will be high. re 2 - 2 3 2 receiver enable. a low input enables the receiver. a high input forces the receiver output into a high impedance state. if re is high with de low, the part will enter a low power shutdown state. de 3 - 3 4 3 driver enable. a high input on de enables the driver. a low input will force the driver outputs into a high impedance state. if de is low with re high, the part will enter a low power shutdown state. di 4 3 4 5 4 driver input. if the driver outputs are enabled (de high), then a low on di forces the driver noninverting output y low and inverting output z high. a high on di, with the driver outputs enabled, forces the driver noninverting output y high and inverting output z low. v l - - - - 5 logic supply: 1.65v v l v cc . bypass with 0.1f ceramic capacitor. powers ro, re, de, di and slo interfaces on LTC2865 only. gnd 5 4 5 6, 7 6 ground. exposed pad 9 9 11 - 13 connect the exposed pads on the dfn and msop packages to gnd slo - - - - 7 slow mode enable. a low input switches the transmitter to the slew rate limited 250kbps max data rate mode. a high input supports 20mbps. y - 5 6 9 8 noninverting driver output for ltc2863, ltc2864, LTC2865. high-impedance when driver disabled or unpowered. z - 6 7 10 9 inverting driver output for ltc2863, ltc2864, LTC2865. high-impedance when driver disabled or unpowered. b 7 7 8 11 10 inverting receiver input (and inverting driver output for ltc2862). impedance is > 96k in receive mode or unpowered. a 6 8 9 12 11 noninverting receiver input (and noninverting driver output for ltc2862). impedance is > 96k in receive mode or unpowered. v cc 8 1 10 14 12 power supply. 3v < v cc < 5.5v. bypass with 0.1f ceramic capacitor to gnd. nc 1, 8, 13 unconnected pins. float or connect to gnd. receiver output voltage vs output current (source and sink) receiver propagation delay vs temperature receiver skew vs temperature t ypical per f or m ance c harac t eris t ics t a = 25c, v cc = v l = 3.3v, unless otherwise noted. output current (absolute value) (ma) 0.0 0.0 receiver output voltage (v) 3.0 2.0 1.0 4.0 5.0 6.0 2.0 4.0 6.0 2862345 g10 8.0 v l = 5.5v v l = 3.3v v l = 2.25v v l = 1.65v v l = 1.65v to 5.5v temperature (c) ?50 46 receiver delay (ns) 52 50 48 54 56 58 0 50 100 2862345 g11 150 v ab = 1.5v c l = 15pf temperature (c) ?50 ?2.6 receiver skew (ns) ?2.2 ?2.4 ?2.0 ?1.8 ?1.6 0 50 100 2862345 g12 150 v ab = 1.5v c l = 15pf 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
9 for more information www.linear.com/ltc2862 b lock dia g ra m s driver mode control logic receiver 2862345 bda gnd *15kv esd di de re ro v cc a* b* driver receiver 2862345 bdb gnd di ro v cc a* b* z* y* *15kv esd driver mode control logic receiver 2862345 bdc gnd di de re ro v cc a* b* z* y* *15kv esd driver mode control logic receiver 2862345 bdd gnd *15kv esd di slo de re ro v cc a* b* z* y* vl ltc 2862 ltc 2864 ltc 2865 ltc 2863 ltc2862 logic inputs mode a, b ro de re 0 0 receive r in active 0 1 shutdown r in high-z 1 0 transceive active active 1 1 transmit active high-z ltc2864, LTC2865: logic inputs mode a, b y, z ro de re 0 0 receive r in high-z active 0 1 shutdown r in high-z high-z 1 0 transceive r in active active 1 1 transmit r in active high-z f unc t ion tables 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
10 for more information www.linear.com/ltc2862 tes t c ircui t s driver di gnd or v cc * r y** z** r 2862345 fo1 v od + ? v oc + ? *LTC2865 only: substitute v l for v cc **ltc2862 only: substitute a, b for y, z driver di gnd or v cc * *LTC2865 only: substitute v l for v cc **ltc2862 only: substitute a, b for y, z y** z** ?60v to 60v 2862345 fo2 i osd + ? receiver b or a a or b v in i in 2862345 fo3 + ? v in r in = i in driver di c l c l y** r diff z** 2862345 fo4 **ltc2862 only: substitute a, b for y, z t skewd 1/2 v o t plhd v cc * 0v di y, z (y?z) t rd 90% 90% 2862345 f04b 10% 10% 0 0 t fd t phld v o *LTC2865 only: substitute v l for v cc figure 1. driver dc characteristics figure 2. driver output short - circuit current figure 3. receiver input current and input resistance figure 4. driver timing measurement 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
11 for more information www.linear.com/ltc2862 t es t circui t s driver c l r l r l y** de z** 2862345 fo5 c l di v cc * or gnd gnd or v cc v cc or gnd *LTC2865 only: substitute v l for v cc **ltc2862 only: substitute a, b for y, z t zld , t zlsd t zhd , t zhsd t hzd , t shdn v cc * 1/2 v cc * v cc v ol v oh 0v 0v de y or z z or y 2862345 f05b t lzd 1/2 v cc 0.5v 0.5v 1/2 v cc *LTC2865 only: substitute v l for v cc receiver c l ro v cm v ab /2 v ab /2 a b 2862345 fo6a t plhr t phlr v ab v cc * ?v ab a?b ro 0 t rr t fr 90% 90% 2862345 f06b 10% 10% 0 1/2 v cc * 1/2 v cc * *LTC2865 only: substitute v l for v cc t skewr = |t plhr ? t phlr | receiver c l r l ro re a b 2862345 fo7a 0v or v cc di = 0v or v cc * v cc or 0v v cc * or gnd *LTC2865 only: substitute v l for v cc t zlr , t zlsr t zhr , t zhsr t hzr , t shdnr v cc * v cc * v ol v oh 0v 0v re ro ro 2862345 f07b t lzr 1/2 v cc * 0.5v 0.5v 1/2 v cc * *LTC2865 only: substitute v l for v cc 1/2 v cc * figure 5. driver enable and disable timing measurements figure 6. receiver propagation delay measurements figure 7. receiver enable / disable time measurements 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
12 for more information www.linear.com/ltc2862 a pplica t ions i n f or m a t ion 60v fault protection the ltc2862-LTC2865 devices answer application needs for overvoltage fault-tolerant rs485/rs422 transceivers operating from 3 v to 5.5 v power supplies. industrial installations may encounter common mode voltages between nodes far greater than the C7 v to 12 v range specified by the rs485 standards. standard rs485 transceivers can be damaged by voltages above their typical absolute maximum ratings of C8 v to 12.5 v. the limited overvoltage tolerance of standard rs485 transceivers makes implementation of effective external protection networks difficult without interfering with proper data network performance within the C7 v to 12 v region of rs485 operation. replacing standard rs485 transceivers with the rugged ltc2862-LTC2865 devices may eliminate field failures due to overvoltage faults without using costly external protection devices. the 60 v fault protection of the ltc2862 series is achieved by using a high- voltage bicmos integrated circuit technology. the naturally high breakdown voltage of this technology provides protection in powered-off and high- impedance conditions. the driver outputs use a progressive foldback current limit design to protect against overvoltage faults while still allowing high current output drive. the ltc2862 series is protected from 60 v faults even with gnd open, or v cc open or grounded. additional precautions must be taken in the case of v cc present and gnd open. the ltc2862 series chip will protect itself from damage, but the chip ground current may flow out through the esd diodes on the logic i/o pins and into associated circuitry. the system designer should examine the susceptibility of the associated circuitry to damage if the condition of a gnd open fault with v cc present is anticipated. the high voltage rating of the ltc2862 series makes it simple to extend the overvoltage protection to higher levels using external protection components. compared to lower voltage rs485 transceivers, external protection devices with higher breakdown voltages can be used, so as not to interfere with data transmission in the presence of large common mode voltages. the typical applications section shows a protection network against faults up to 360v peak, while still maintaining the extended 25v common mode range on the signal lines. 25v extended common mode range to further increase the reliability of operation and extend functionality in environments with high common mode voltages due to electrical noise or local ground potential differences due to ground loops, the ltc2862-LTC2865 devices feature an extended common mode operating range of C25 v to 25 v. this extended common mode range allows the ltc2862-LTC2865 devices to transmit and receive under conditions that would cause data errors and possible device damage in competing products. 15kv esd protection the ltc2862 series devices feature exceptionally robust esd protection . the transceiver interface pins (a,b,y,z) feature protection to 15 kv hbm with respect to gnd without latchup or damage, during all modes of operation or while unpowered. all the other pins are protected to 8kv hbm to make this a component capable of reliable operation under severe environmental conditions. driver the driver provides full rs485/rs422 compatibility. when enabled, if di is high, yCz is positive for the full-duplex devices ( ltc2863-LTC2865) and aCb is positive for the half-duplex device (ltc2862). when the driver is disabled, both outputs are high- impedance. for the full-duplex devices, the leakage on the driver output pins is guaranteed to be less than 30a over the entire common mode range of C25 v to 25 v. on the half-duplex ltc2862, the impedance is dominated by the receiver input resistance, r in . driver overvoltage and overcurrent protection the driver outputs are protected from short circuits to any voltage within the absolute maximum range of C60 v to 60v. the maximum current in a fault condition is 250ma. the driver includes a progressive foldback current limiting circuit that continuously reduces the driver current limit with increasing output fault voltage. the fault current is less than 15ma for fault voltages over 40v. all devices also feature thermal shutdown protection that disables the driver and receiver in case of excessive power dissipation (see note 4). 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
13 for more information www.linear.com/ltc2862 a pplica t ions i n f or m a t ion full failsafe operation when the absolute value of the differential voltage between the a and b pins is greater than 200 mv with the receiver enabled, the state of ro will reflect the polarity of ( aCb). these parts have a failsafe feature that guarantees the receiver output will be in a logic 1 state ( the idle state) when the inputs are shorted, left open, or terminated but not driven, for more than about 3 s. the delay allows normal data signals to transition through the threshold region without being interpreted as a failsafe condition. this failsafe feature is guaranteed to work for inputs spanning the entire common mode range of C25v to 25v. most competing devices achieve the failsafe function by a simple negative offset of the input threshold voltage. this causes the receiver to interpret a zero differential voltage as a logic 1 state. the disadvantage of this approach is the input offset can introduce duty cycle asymmetry at the receiver output that becomes increasingly worse with low input signal levels and slow input edge rates. other competing devices use internal biasing resistors to create a positive bias at the receiver inputs in the absence of an external signal. this type of failsafe biasing is ineffective if the network lines are shorted, or if the network is terminated but not driven by an active transmitter. the positive and negative thresholds. if this condition persists for more than about 3 s the failsafe condition is asserted and the ro pin is forced to the logic 1 state. this circuit provides full failsafe operation with no negative impact to receiver duty cycle symmetry, as shown in figure 8. the input signal in figure 8 was obtained by driving a 10mbps rs485 signal through 1000 feet of cable, thereby attenuating it to a 200 mv signal with slow rise and fall times. good duty cycle symmetry is observed at ro despite the degraded input signal. enhanced receiver noise immunity an additional benefit of the fully symmetric receiver thresholds is enhanced receiver noise immunity. the differential input signal must go above the positive threshold to register as a logic 1 and go below the negative threshold to register as a logic 0. this provides a hysteresis of 150mv ( typical) at the receiver inputs for any valid data signal . ( an invalid data condition such as a dc sweep of the receiver inputs will produce a different observed hysteresis due to the activation of the failsafe circuit.) competing devices that employ a negative offset of the input threshold voltage generally have a much smaller hysteresis and subsequently have lower receiver noise immunity. rs485 network biasing rs485 networks are usually biased with a resistive divider to generate a differential voltage of 200 mv on the data lines, which establishes a logic 1 state ( the idle state) when all the transmitters on the network are disabled. the values of the biasing resistors are not fixed, but depend on the number and type of transceivers on the line and the number and value of terminating resistors. therefore, the values of the biasing resistors must be customized to each specific network installation, and may change if nodes are added to or removed from the network. the internal failsafe feature of the ltc2862-LTC2865 eliminates the need for external network biasing resistors provided they are used in a network of transceivers with similar internal failsafe features. the ltc2862-LTC2865 transceivers will operate correctly on biased, unbiased, or under-biased networks. figure 8. duty cycle of balanced receiver with 200 mv 10 mbps input signal a, b 200mv/div a?b 200mv/div 40ns/div 2862345 f08 ro 1.6v/div the ltc2862 series uses fully symmetric positive and negative receiver thresholds ( typically 75 mv) to maintain good duty cycle symmetry at low signal levels. the failsafe operation is performed with a window comparator to determine when the differential input voltage falls between 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
14 for more information www.linear.com/ltc2862 hi-z state the receiver output is internally driven high ( to v cc or v l ) or low ( to gnd) with no external pull-up needed. when the receiver is disabled the ro pin becomes hi-z with leakage of less than 5a for voltages within the supply range. high receiver input resistance the receiver input load from a or b to gnd for the ltc2863, ltc2864, and LTC2865 is less than one-eighth unit load, permitting a total of 256 receivers per system without exceeding the rs485 receiver loading specification. all grades of the ltc2862 and the h- and mp-grade devices of the ltc2863, ltc2864, and LTC2865 have an input load less than one-seventh unit load over the complete temperature range of C40 c to 125 c. the increased input load specification for these devices is due to increased junction leakage at high temperature and the transmitter circuitry sharing the a and b pins on the ltc2862. the input load of the receiver is unaffected by enabling/ disabling the receiver or by powering/unpowering the part. supply current the unloaded static supply currents in these devices are low typically 900 a for non slew limited devices and 3.3ma for slew limited devices. in applications with resistively terminated cables, the supply current is dominated by the driver load. for example, when using two 120? terminators with a differential driver output voltage of 2 v, the dc load current is 33 ma, which is sourced by the positive voltage supply. power supply current increases with toggling data due to capacitive loading and this term can increase significantly at high data rates. a plot of the supply current vs data rate is shown in the typical performance characteristics of this data sheet. during fault conditions with a positive voltage larger than the supply voltage applied to the transmitter pins, or during transmitter operation with a high positive common mode voltage, positive current of up to 80 ma may flow from the transmitter pins back to v cc . if the system power supply or loading cannot sink this excess current, a 5.6v 1w 1n4734 zener diode may be placed between v cc and gnd to prevent an overvoltage condition on v cc . there are no power-up sequence restrictions on the LTC2865. however, correct operation is not guaranteed for v l > v cc . shutdown mode delay the ltc2862, ltc2864, and LTC2865 feature a low power shutdown mode that is entered when both the driver and the receiver are simultaneously disabled ( pin de low and re high). a shutdown mode delay of approximately 250ns (not tested in production) is imposed after this state is received before the chip enters shutdown. if either de goes high or re goes low during this delay, the delay timer is reset and the chip does not enter shutdown. this reduces the chance of accidentally entering shutdown if de and re are driven in parallel by a slowly changing signal or if de and re are driven by two independent signals with a timing skew between them. this shutdown mode delay does not affect the outputs of the transmitter and receiver, which start to switch to the high impedance state upon the reception of their respec- tive disable signals as defined by the parameters t shdnd and t shdnr . the shutdown mode delay affects only the time when all the internal circuits that draw dc power from v cc are turned off. high speed considerations a ground plane layout with a 0.1 f bypass capacitor placed less than 7 mm away from the v cc pin is recommended. the pc board traces connected to signals a/b and z/y should be symmetrical and as short as possible to maintain good differential signal integrity. to minimize capacitive effects, the differential signals should be separated by more than the width of a trace and should not be routed on top of each other if they are on different signal planes. care should be taken to route outputs away from any sensitive inputs to reduce feedback effects that might cause noise, jitter, or even oscillations. for example, in the full-duplex devices, di and a/b should not be routed near the driver or receiver outputs. the logic inputs have a typical hysteresis of 100 mv to provide noise immunity. fast edges on the outputs can cause glitches in the ground and power supplies which are a pplica t ions i n f or m a t ion 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
15 for more information www.linear.com/ltc2862 exacerbated by capacitive loading. if a logic input is held near its threshold ( typically v cc /2 or v l /2), a noise glitch from a driver transition may exceed the hysteresis levels on the logic and data input pins, causing an unintended state change. this can be avoided by maintaining normal logic levels on the pins and by slewing inputs faster than 1v/ s. good supply decoupling and proper driver termination also reduce glitches caused by driver transitions. rs485 cable length vs data rate many factors contribute to the maximum cable length that can be used for rs 485 or rs 422 communication , including driver transition times , receiver threshold , duty cycle distortion , cable properties and data rate . a typical curve of cable length versus maximum data rate is shown in figure 9. various regions of this curve reflect different performance limiting factors in data transmission. at frequencies below 100 kbps , the maximum cable length is determined by dc resistance in the cable . in this example , a cable longer than 4000 ft will attenuate the signal at the far end to less than what can be reliably detected by the receiver . for data rates above 100 kbps the capacitive and inductive properties of the cable begin to dominate this relationship . t he attenuation of the cable is frequency and length dependent , resulting in increased rise and fall times at the far end of the cable . at high data rates or long cable a pplica t ions i n f or m a t ion lengths , these transition times become a significant part of the signal bit time . jitter and intersymbol interference aggravate this so that the time window for capturing valid data at the receiver becomes impossibly small . the boundary at 20 mbps in figure 9 represents the guaranteed maximum operating rate of the ltc 2862 series . the dashed vertical line at 10 mbps represents the specified maximum data rate in the rs 485 standard . this boundary is not a limit , but reflects the maximum data rate that the specification was written for . it should be emphasized that the plot in figure 9 shows a typical relation between maximum data rate and cable length . results with the ltc 2862 series will vary , depending on cable properties such as conductor gauge , characteristic impedance , insulation material , and solid versus stranded conductors . low emi 250kbps data rate the ltc2862-2, ltc2863-2, and the ltc2864-2 feature slew rate limited transmitters for low electromagnetic interference ( emi) in sensitive applications. in addition, the LTC2865 has a logic-selectable 250 kbps transmit rate. the slew rate limit circuit maintains consistent control of transmitter slew rates across voltage and temperature to ensure low emi under all operating conditions. figure 10 demonstrates the reduction in high frequency content achieved by the 250 kbps mode compared to the 20mbps mode. figure 9. cable length vs data rate ( rs 485/ rs 422 standard shown in vertical solid line ) figure 10. high frequency emi reduction of slew limited 250 kbps mode compared to non slew limited 20 mbps mode data rate (bps) 10k 10 cable length (ft) 100 1k 10k 100k 1m 10m 2862345 f09 100m low emi mode slo = gnd rs485 standard spec frequency (mhz) 0 ?120 y?z (non slew limited) (db) ?40 ?60 ?80 ?100 ?20 0 20 ?60 y?z (slew limited) (db) 20 0 ?20 ?40 40 60 80 2 4 6 8 10 2862345 f10 12 non slew limited slew limited 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
16 for more information www.linear.com/ltc2862 the 250 kbps mode has the added advantage of reducing signal reflections in an unterminated network, and there- by increasing the length of a network that can be used without termination. using the rule of thumb that the rise time of the transmitter should be greater than four times the one-way delay of the signal, networks of up to 140 feet can be driven without termination. profibus compatible interface profibus is an rs485-based field bus. in addition to the specifications of tia/eia-485-a, the profibus specification contains additional requirements for cables, interconnects, line termination, and signal levels. the following discussion applies to the profibus type a cables with associated connectors and termination. the type a cable is a twisted pair shielded cable with a characteristic impedance of 135 ? to 165? and a loop resistance of < 110/km. the LTC2865 family of rs485 transceivers may be used in profibus compatible equipment if the following considerations are implemented . ( please refer to the schematic of the profibus compatible interface in the typical applications section.) 1. the polarity of the profibus signal is opposite to the polarity convention used in this data sheet. the pro - fibus b wire is driven by a non-inverted signal, while the a wire is driven by an inverted signal. therefore, it is necessary to swap the output connections from the transceiver. pin a is connected to the profibus b wire, and pin b is connected to the profibus a wire. 2. each end of the profibus line is terminated with a 220 resistor between b and a, a 390 pull-up resis - tor between b and v cc , and a 390 pull-down resistor be- tween a and gnd. this provides suitable termination for the 150 twisted pair transmission cable. 3. the peak to peak differential voltage v od received at the end of a 100 m cable with the cable and termina- tions described above must be greater than 4 v and less than 7 v. the LTC2865 family produces signal levels in excess of 7 v when driving this network directly. 8.2? resistors may be inserted between the a and b pins of the transceiver and the b and a pins of the profibus cable to attenuate the transmitted signal to meet the profibus upper limit of 7 v while still providing enough drive strength to meet the lower limit of 4v. 4. the LTC2865 family transceiver should be powered by a 5% tolerance 5 v supply (4.75v to 5.25 v) to ensure that the profibus v od tolerances are met. auxiliary protection for iec surge, eft and esd an interface transceiver used in an industrial setting may be exposed to extremely high levels of electrical overstress due to phenomena such as lightning surge, electrical fast transient ( eft) from switching high current inductive loads, and electrostatic discharge ( esd) from the discharge of electrically charged personnel or equip- ment. test methods to evaluate immunity of electronic equipment to these phenomenon are defined in the iec standards 61000-4-2, 61000-4-4, and 61000-4-5, which address esd, eft, and surge, respectively. the transi- ents produced by the eft and particularly the surge tests contain much more energy than the esd transients. the LTC2865 family is designed for high robustness against esd, but the on-chip protection is not able to absorb the energy associated with the 61000-4-5 surge transients. therefore, a properly designed external protection network is necessary to achieve a high level of surge protection, and can also extend the esd and eft performance of the LTC2865 family to extremely high levels. in addition to providing surge, eft and esd protection, an external network should preserve or extend the ability of the LTC2865 family to withstand overvoltage faults , operate over a wide common mode, and communicate at high frequencies. in order to meet the first two requirements, protection components with suitably high conduction voltages must be chosen. a means to limit current must be provided to prevent damage in case a secondary protection device or the esd cell on the LTC2865 family fires and conducts. the capacitance of these components must be kept low in order to permit high frequency communication over a network with multiple nodes . meeting the requirements for conducting very high energy electrical transients while maintaining high hold- off voltages and low capacitance is a considerable challenge. a pplica t ions i n f or m a t ion 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
17 for more information www.linear.com/ltc2862 a pplica t ions i n f or m a t ion a protection network shown in the typical applications section ( network for iec level 4 protection against surge, eft and esd) meets this challenge. the network provides the following protection: ? iec 61000-4-2 esd level 4: 30 kv contact, 30 kv air ( line to gnd, direct discharge to bus pins with transceiver and protection circuit mounted on a ground referenced test card per figure 4 of the standard) ? iec 61000-4-4 eft level 4: 5kv ( line to gnd, 5khz repetition rate , 15 ms burst duration , 60 second test duration, discharge coupled to bus pins through 100pf capacitor per paragraph 7.3.2 of the standard) ? iec 61000-4-5 surge level 4: 5kv ( line to gnd, line to line, 8/20 s waveform, each line coupled to generator through 80 resistor per figure 14 of the standard) this protection circuit adds only ~8 pf of capacitance per line ( line to gnd), thereby providing an extremely high level of protection without significant impact to the performance of the LTC2865 family transceivers at high data rates. the gas discharge tubes ( gdts) provide the primary pro- tection against electrical surges. these devices provide a very low impedance and high current carrying capability when they fire, safely discharging the surge current to gnd. the transient blocking units ( tbus) are solid state devices that switch from a low impedance pass through state to a high impedance current limiting state when a specified current level is reached. these devices limit the current and power that can pass through to the secondary protection. the secondary protection consists of a bidirectional thyristor, which triggers above 35 v to protect the bus pins of the LTC2865 family transceiver. the high trigger voltage of the secondary protection maintains the full 25 v common mode range of the receivers. the final component of the network is the metal oxide varistors (movs) which are used to clamp the voltage across the tbus to protect them against fast esd and eft transients which exceed the turn-on time of the gdt. the high performance of this network is attributable to the low capacitance of the gdt and thyristor primary and secondary protection devices. the high capacitance mov floats on the line and is shunted by the tbu, so it contributes no appreciable capacitive load on the signal. profibus compatible line interface typical a pplica t ions ro re de di 8.2 2862345 ta02 a* b* * the polarity of a and b in this data sheet is opposite the polarity defined by profibus. v cc (4.75v to 5.25v) gnd ltc2862-1 8.2 390 4v p-p v od 7v p-p at 12mbps 220 390 b wire a wire b wire a wire v cc 390 220 390 v cc 100m 5.5/wire v od 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
18 for more information www.linear.com/ltc2862 typical a pplica t ions ro de di r d ro de di/ v cc b a gnd 2862345 ta04 ?a? ?b? 5v ltc2862 i1 i2 failsafe o application ( idle state = logic o) bidirectional 60 v 20 mbps level shifter / isolator di gnd v cc v cc ro ltc2863-1 v cc r1 r1 r2 r2 60v c c a b r1 y z data out 2 r1 = 100k 1%. place r1 resistors near a and b pins. r2 = 10k c = 47pf, 5%, 50 wvdc. may be omitted for data rates 100kbps. data in 1 data out 1 data in 2 v cc ro ltc2863-1 y z di gnd c a b 2862345 ta03 r1 c 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
19 for more information www.linear.com/ltc2862 .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0? 8 typ .008 ? .010 (0.203 ? 0.254) so8 rev g 0212 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc 1 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 8 7 6 5 .189 ? .197 (4.801 ? 5.004) note 3 .228 ? .244 (5.791 ? 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) 4. pin 1 can be bevel edge or a dimple s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610 rev g) p acka g e descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
20 for more information www.linear.com/ltc2862 dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698 rev c) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (dd8) dfn 0509 rev c 0.25 0.05 2.38 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 (2 sides) 2.10 0.05 0.50 bsc 0.70 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc p acka g e descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
21 for more information www.linear.com/ltc2862 1 n 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 14 13 .337 ? .344 (8.560 ? 8.738) note 3 .228 ? .244 (5.791 ? 6.197) 12 11 10 9 5 6 7 n/2 8 .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0 ? 8 typ .008 ? .010 (0.203 ? 0.254) s14 rev g 0212 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc .245 min n 1 2 3 n/2 .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) 4. pin 1 can be bevel edge or a dimple s package 14-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610 rev g) p acka g e descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
22 for more information www.linear.com/ltc2862 dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer p acka g e descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
23 for more information www.linear.com/ltc2862 de/ue package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695 rev d) 4.00 0.10 (2 sides) 3.00 0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.50 ref 1 6 12 7 pin 1 notch r = 0.20 or 0.35 45 chamfer pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (ue12/de12) dfn 0806 rev d 2.50 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 3.30 0.10 0.25 0.05 0.50 bsc 1.70 0.05 3.30 0.05 0.50 bsc 0.25 0.05 p acka g e descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
24 for more information www.linear.com/ltc2862 p acka g e descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (mse12) 0213 rev g 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ?0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail ?b? 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev g) mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev g) 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
25 for more information www.linear.com/ltc2862 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 03/13 added mp-grade to data sheet updated s8 and s package 2, 4 17, 19 b 01/14 changed i ccs for h-/mp-grade. added v l supply current vs data rate graph. added shutdown mode delay section. added profibus compatible interface section, auxiliary protection for iec surge, eft and esd section, and profibus compatible line interface schematic. replaced rs485 network with 120v ac line fault protection schematic with network for iec level 4 protection against surge, eft and esd plus 360v overvoltage protection schematic. 4 7 14 16, 17 26 c 03/14 changed part marking for de package 4 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865
26 for more information www.linear.com/ltc2862 ? linear technology corporation 2011 lt 0314 rev c ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2862 r ela t e d p ar t s typical a pplica t ion part number description comments lt1785, lt1791 60v fault protected rs485/rs422 transceivers 60v tolerant, 15kv esd, 250kbps ltc2850-53 3.3v 20mbps 15kv rs485 transceivers up to 256 transceivers per bus ltc2854, ltc2855 3.3v 20mbps rs485 transceivers with integrated switchable termination 25kv esd (ltc2854), 15kv esd (ltc2855) ltc2856-1 family 5v 20mbps and slew rate limited rs485 transceivers 15kv esd ltc2859, ltc2861 5v 20mbps rs485 transceivers with integrated switchable termination 15kv esd ltc1535 isolated rs485 transceiver 2500v rms isolation, requires external transceiver ltm2881 complete 3.3v isolated rs485/rs422 module ? transceiver + power 2500v rms isolation with integrated isolated dc/dc converter, 1w power, low emi, 15kv esd, 30kv/s common mode transient immunity network for iec level 4 protection against surge , eft and esd plus 360 v overvoltage protection 2862345 ta05 v cc de scr gdt scr a b di ltc2862-1 gdt: bourns 2031-42t-sm; 420v gas discharge tube tbu: bourns tbu-ca085-300-wh; 850v transient blocking unit mov: bourns mov-7d391k; 390v 25j metal oxide varistor scr: bourns tisp4p035l1nr-s; 35v bidirectional thyristor ro t r gnd re mov mov tbu tbu gdt gnd rs485 a (external) rs485 b (external) 2862345fc ltc2862/ltc2863/ ltc2864/LTC2865

▲Up To Search▲

Price & Availability of LTC2865

	To Download LTC2865 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .